Boyang Zhang

• Worked on GPU-accelerated Statistical Static Timing Analysis.

• Designed PASTA, a fast task-graph partitioner for static timing analysis (STA), with both a parallel CPU version (C-PASTA ISPD’24) and a GPU version (G-PASTA DAC’24). PASTA aims to reduce task-scheduling overhead by partitioning the original task graph into a smaller graph without affecting too much its parallelism.
• Designed iTAP, an incremental task graph partitioner for STA built on top of PASTA (ASP-DAC’25). iTAP aims to further reduce the partitionig runtime by incrementally updating the partitioned task graph, avoiding fully repartition the entire graph when only a small portion of the graph changes.
• Implemented an efficient GPU kernel for Finite-Difference Time-Domain (FDTD) simulation that applies diamond tiling to exploit temporal data reuse in shared memory, achieving ~40% speedup over a state-of-the-art implementation on a 4M-cell problem.
• Designed G-STAR, a GPU-accelerated statistical static timing analysis algorithm using level-by-level replication. G-STAR aims to enable efficient levelized data propagation for memory-bound workloads whose full level list cannot fit in GPU memory at once.

• Implemented various task graph partitioners (Repcut, Vivek’s, GDCA) to speed up the update timing process in OpenTimer.

• Implemented R-tree motion planning algorithm for 2-D space searching in MATLAB.
• Implemented a simple five-layer CNN inference phrase based on the systolic array architecture on a PYNQ-Z1 FPGA board. Data is pre-trained in PC with PyTorch and loaded into DRAM through UART. The CNN computation part is implemented in Verilog on the FPGA part of the board. Data transfer is controlled by the SoC ZYNQ processor programmed in C.
• Implemented a parser in JavaScript with RapidWright library to parse the placement information in Xilinx’s Vivado Design Tools. The output of the parser, which contains the placement information from Vivado, can be used as input to academic placers to improve the placement results from Vivado. The improved placement results from the academic placers can then be inputted back to Vivado to finish the later routing process.

ECE 376 Electrical and Electronic Circuits.

• Led the course discussion.

ECE 14:332:231 Digital Logic Design.

• Designed the lab materials and policies.
• Designed the final project (A simple RISC-V architecture written in SystemVerilog).